C implants for improved SiGe bipolar yield

ABSTRACT

A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region, the sub-collector region, the extrinsic base regions, and the collector-base junction region. In a preferred embodiment each of the aforesaid regions include C implants.

FIELD OF THE INVENTION

[0001] The present invention relates to semiconductor heterojunctionbipolar transistors, and more particularly to a method of fabricating aSiGe heterojunction bipolar transistor in which the SiGe bipolar yieldis substantially improved by suppressing dislocations that causecollector-emitter (CE) leakage or shorts, or collector-base (CB) leakageor shorts.

BACKGROUND OF THE INVENTION

[0002] Significant growth in both high-frequency wired and wirelessmarkets has introduced new opportunities where compound semiconductorssuch as SiGe have unique advantages over bulk complementary metal oxidesemiconductor (CMOS) technology. With the rapid advancement ofepitaxial-layer pseudomorphic SiGe deposition processes, epitaxial-baseSiGe heterojunction bipolar transistors have been integrated withmainstream CMOS development for wide market acceptance, providing theadvantages of SiGe technology for analog and RF circuitry whilemaintaining the full utilization of the advanced CMOS technology basefor digital logic circuitry.

[0003] It is well documented that excess interstitials created byimplant damage cause the formation of dislocations in the collector andemitter regions of bipolar devices. When the dislocations extend betweenthe collector and emitter regions, bipolar pipe shorts, i.e.,collector-emitter shorts, may occur. In such a context, SiGe bipolaryield can be reduced by as much as 20 to 50% for dislocationsoriginating in the collector region.

[0004] The incorporation of C, carbon, into SiGe heterojunction deviceshas been carried out in the prior art to prevent the out-diffusion ofboron into the base region. For example, it is known that the transientenhanced diffusion of boron is strongly suppressed in carbon-richsilicon layers; See, for example, H. J. Osten, et al., “Carbon DopedSiGe Heterojunction Bipolar Transistors for High FrequencyApplications”, IEEEBTCM 7.1, 109. Boron diffusion in silicon occurs viaan interstitial mechanism and is proportional to the concentration ofsilicon self-interstitials. Diffusion of carbon out of the carbon-richregions causes an undersaturation of silicon self-interstitials. As aresult, the diffusion of boron in these regions will be suppressed.Despite being capable of suppressing the diffusion of boron, prior artmethods that incorporate C into the SiGe heterojunction bipolarstructure do not prevent bipolar pipe shorts from occurring. Thus, priorart methods do not improve the SiGe bipolar yield.

[0005] In view of the SiGe bipolar yield problem mentioned above, thereis a continued need for providing a new and improved method forimproving SiGe heterojunction bipolar yield due to dislocationsoriginating in the pedestal and collector regions of the device.

SUMMARY OF THE INVENTION

[0006] One object of the present invention is to provide a method offabricating a SiGe heterojunction bipolar transistor wherein improvedSiGe bipolar yield is achieved.

[0007] Another object of the present invention is to provide a method offabricating a SiGe heterojunction bipolar transistor in which the amountof dislocations present in the device is substantially reduced therebyavoiding pipe shorts.

[0008] A further object of the present invention is to provide a methodof fabricating a SiGe heterojunction bipolar transistor using processingsteps that are compatible with existing bipolar and CMOS processingsteps.

[0009] These and other objects and advantages are achieved in thepresent invention by implanting carbon, C, into certain predeterminedregions of the SiGe bipolar transistor. Specifically, applicants havedetermined that by incorporating C (via implantation only) into thesub-collector, the collector, the extrinsic base and the collector-basejunction region of a bipolar device, separately or in any combination,improved SiGe bipolar yield can be obtained. The carbon implant(s) maybe carried out by blanket or masked implant techniques well known tothose skilled in the art.

[0010] The greatest enhancement and most preferred embodiment of thepresent invention is obtained when all the C implants, as definedhereinabove, are employed. The improved SiGe bipolar yield obtained bythe present invention is a significant advancement in this art since itresults in a device having substantially less pipe shorts thanheretofore possible with prior art SiGe heterojunction bipolar devices.

[0011] Broadly speaking, the present invention includes a method forimproving the SiGe bipolar yield which comprises the steps of:

[0012] (a) providing a structure which includes at least a bipolardevice region, said bipolar device region comprising at least acollector region formed over a sub-collector region, and a SiGe layerformed over said collector and subcollector regions, said SiGe layercomprising at least an intrinsic base region and a collector-basejunction region, wherein said intrinsic base region is abutted byextrinsic base regions; and

[0013] (b) implanting C into at least one region of said structureselected from said collector, said sub-collector, said extrinsic baseregions and said collector-base junction region.

[0014] In one embodiment of the present invention, the SiGe layer isgrown utilizing a non-selective epi process. In this embodiment, theSiGe layer would include extrinsic base regions abutting the intrinsicbase region. In other embodiments, the SiGe layer is formed withoutextrinsic base regions. In that embodiment, the extrinsic base regions,which may or may not include germanium, are formed separately from theSiGe layer.

[0015] In a preferred embodiment of the present invention, the method ofthe present invention comprises the steps of:

[0016] (a) providing a structure which includes at least a bipolardevice region, said bipolar device region comprising at least acollector region formed over a sub-collector region;

[0017] (b) implanting C into said collector and said sub-collectorregions;

[0018] (c) forming a SiGe layer on said bipolar device region, said SiGelayer comprising at least an intrinsic base region and a collector-basejunction region, wherein said intrinsic base region is abutted byextrinsic base regions;

[0019] (d) implanting C into said extrinsic base regions;

[0020] (e) forming an insulator layer on said SiGe layer;

[0021] (f) providing an emitter opening in said insulator layer so as toexpose a portion of said intrinsic base region and implanting C throughsaid emitter opening and through the exposed portion of said intrinsicbase region into the collector-base junction region; and

[0022] (g) forming an emitter polysilicon region on said insulatorlayer, including in said emitter opening.

[0023] A further aspect of the present invention relates to a SiGeheterojunction bipolar transistor that has improved SiGe bipolar yield.Specifically, the inventive SiGe heterojunction bipolar transistorcomprises:

[0024] a semiconductor substrate of a first conductivity type includingat least a sub-collector region and a collector region;

[0025] a SiGe base layer formed on said substrate, said SiGe base layercomprising at least collector-base junction region formed over thecollector region and an intrinsic base region, wherein said intrinsicbase region is abutted by extrinsic base regions; and

[0026] an emitter region formed on a portion of said intrinsic baseregion, said emitter region comprising at least an emitter polysiliconregion, wherein at least one region of said structure selected from saidcollector, said sub-collector, said extrinsic base regions and saidcollector-base junction region includes a C implant.

[0027] In another preferred embodiment of the present invention, thebipolar transistor comprises:

[0028] a semiconductor substrate of a first conductivity type includingat least a sub-collector region and a collector region which are bothdoped with implanted C;

[0029] a SiGe base layer formed on said substrate, said SiGe base layercomprising at least a collector-base junction region formed over thecollector region, an intrinsic base region and extrinsic base regionsabutting said intrinsic base region, wherein said collector-basejunction region and said extrinsic base regions are doped with implantedC; and

[0030] an emitter region formed on a portion of said intrinsic baseregion, said emitter region comprising at least an emitter polysiliconregion.

[0031] Note that each of the C-doped regions is formed by implanting Cinto the specific region by utilizing the method of the presentinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032]FIG. 1 is a cross-sectional view of the inventive SiGeheterojunction bipolar transistor which includes C incorporated into thecollector, sub-collector, and extrinsic base regions and/orcollector-base junction region of the device.

[0033] FIGS. 2-7 are cross-sectional views which shown the structure ofFIG. 1 through various processing steps of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0034] The present invention which is related to the use of C implantsfor improving SiGe bipolar yield will now be described in more detail byreferring to FIGS. 1-7 and the discussion that appears hereinbelow. Itis noted that in the drawings like and corresponding elements arereferred to by like reference numerals. Also, for simplicity, only onebipolar device region is shown in the drawings. Other bipolar deviceregions as well as digital logic circuitry may be formed adjacent to thebipolar device region depicted in the drawings.

[0035] Before discussing the present invention in detail, it is notedthat the drawings depict the preferred embodiment of the inventionwherein the SiGe layer is formed with extrinsic base regions abuttingthe intrinsic base regions. In this embodiment the extrinsic baseregions are formed by a non-selective epi deposition process. Inaddition to this embodiment, the present invention also contemplatesSiGe layers in which the extrinsic base regions are formed separatelyfrom the SiGe layer. Also, note that in the description that followsimplantation of C occurs in all four regions, i.e., the collector,sub-collector, extrinsic base regions and said collector-base junctionregion. Such C implantation into all four regions represents the mostpreferred embodiment of the present invention. The present invention ishowever not limited to C implants into each of these four regions.Instead, in the present invention, at least one of the regions mustinclude C implants.

[0036] Reference is first made to FIG. 1 which represents across-sectional view of the inventive SiGe heterojunction bipolartransistor. Specifically, the SiGe heterojunction bipolar transistorcomprises semiconductor substrate 10 of a first conductivity type (N orP), sub-collector region 14 and collector region 16 which are both dopedwith C via implantation. Isolation regions 12 which are also present inthe structure define the outer boundaries of the bipolar device regionand serve to isolate the bipolar device region shown in FIG. 1 fromadjacent device regions (not shown).

[0037] The SiGe bipolar transistor of FIG. 1 also includes SiGe baselayer 20 formed on substrate 10 as well as on isolation regions 12. Inaccordance with the present invention, the SiGe base layer includespolycrystalline Si regions 24 that are formed predominately overisolation regions 12, and single-crystal SiGe region 22, which includesextrinsic SiGe base regions 29, intrinsic SiGe base region 26, andcollector-base junction region 27, also referred to in the art as thepedestal region of the device, formed predominately over sub-collectorregion 14. In accordance with a preferred embodiment of the presentinvention, the collector-base junction region, and the extrinsic baseregions are both doped with C via implantation. Note that the solid lineseparating each polycrystalline SiGe region from the single-crystal SiGeregion is referred to in the art as a facet region.

[0038] The bipolar transistor of FIG. 1 also comprises emitter region 28which includes patterned insulator layer 30 which has an emitter openingformed therein and a region of emitter polysilicon 32 formed on saidpatterned insulator layer as well as in said emitter opening. Theemitter polysilicon is typically doped N⁺. Note that after formation ofthe emitter polysilicon, dopant from the emitter polysilicon is diffusedinto the intrinsic base region forming emitter diffusion region 34 inthe intrinsic base region 26.

[0039] It is noted that the bipolar transistor shown in FIG. 1 hasimproved SiGe bipolar yield because the C implants in the aboveidentified regions, i.e., sub-collector, collector, extrinsic baseand/or collector-base junction region, reduce the number of dislocationsthat are present in the structure. Note, that it is possible to haveimproved bipolar yield (i.e., emitter-base or emitter-collector leakageyield) when at least one of the above-mentioned regions is doped with Cimplants; however the greatest affect is observed when all the regionsinclude C implants. In the present invention, bipolar yield may beimproved as much as 20 to 50%; therefore the present invention providesan improved structure compared with prior art SiGe bipolar transistorswhich do not contain C implants in the collector, sub-collector,extrinsic base regions and/or the collector-base junction region.

[0040] The method and various materials that are employed in forming theSiGe heterojunction bipolar transistor shown in FIG. 1 will now bedescribed in more detail. Reference is first made to FIG. 2 which showsthe bipolar device region of an initial structure that is employed inthe present invention. The initial structure shown in FIG. 2 comprisessubstrate 10 having sub-collector region 14, collector region 16 andisolation regions 12 formed therein.

[0041] The structure shown in FIG. 2 is fabricated using conventionalprocessing steps that are well known to those skilled in the art.Moreover, conventional materials that are also well known in the art areused in fabricating the same. For example, substrate 10 is composed ofany semiconducting material including but not limited to: Si, Ge, SiGe,GaAs, InAs, InP and all other III/V compound semiconductors. Layeredsubstrates comprising the same or different semiconducting material,e.g., Si/Si or Si/SiGe, are also contemplated herein. Of thesesemiconducting materials, it is preferred that substrate 10 be composedof Si. As mentioned above, the substrate may be a N-type substrate or aP-type substrate depending on the type of device to be subsequentlyformed.

[0042] Sub-collector region 14 is formed in, or alternatively on thesubstrate by using any well known technique that is capable of forming asub-collector region in such a structure. Thus, the sub-collector regioncan be formed via implantation or by an epitaxial growth process. Notethat the drawings depict a sub-collector region that is formed into thesubstrate via ion implantation. Isolations regions 12 are then formed byeither using a conventional local oxidation of silicon (LOCOS) processor by utilizing lithography, etching and trench isolation filling.

[0043] Following the formation of isolation regions in the substrate,collector region 16 is then formed in the bipolar device region (betweenthe two isolation regions shown in FIG. 1) utilizing conventional ionimplantation and activating annealing processes that are well known tothose skilled in the art. The activating annealing process is typicallycarried out at a temperature of about 950° C. or above for a time ofabout 30 seconds or less.

[0044] At this point of the inventive process, the bipolar device regionshown in the drawings may be protected by forming a protective materialsuch as Si₃N₄ thereon, and conventional processing steps which arecapable of forming adjacent device regions can be performed. Aftercompletion of the adjacent device regions and subsequent protectionthereof, the inventive process continues. It should be noted that insome embodiments, the adjacent device regions are formed aftercompletely fabricating the bipolar transistor.

[0045] The next step of the inventive process is shown in FIG. 3.Specifically, FIG. 3 shows the ion implantation of C into sub-collectorregion 14 and collector region 16. The source of carbon used forimplanting these regions is a C-containing material such as CO₂ or anyother C-containing gas source. This first C implantation step which maybe carried out utilizing a one or two-step process is carried out usinga C dose of from about 1E13 to about 1E16 cm⁻². An implantation energyof from about 5 to about 200 keV is employed for implanting C into thecollector region, whereas an energy of from about 10 to about 1000 keVis employed for implanting C into the sub-collector region. Morepreferably, this first C implantation step is carried out using a C doseof about 1E14 cm⁻² and an implantation energy of about 20 keV for thecollector region and about 400 keV for the sub-collector region. The Csource may be used neat (i.e., non-mixed), or it may be mixed with aninert gas such as He or Ar. These implants may be blanket or maskedusing techniques well known to those skilled in the art. In someembodiments, it is possible to omit implanting C into the collector andsubcollector regions.

[0046] Note that the C implant into the sub-collector region may occurduring formation of the isolation regions or may occur after formationof the isolation regions, as is shown herein. Insofar as the collectorregion is concerned, the collector region is typically implanted with Cafter the adjacent devices have been formed and protected.

[0047] Applicants have determined that the first C implant stepmentioned above allows for a carbon source to be present in thestructure that will reduce the level of free interstitials formingdislocations at the base of the SiGe layer. Without wishing to be boundby any theory, the mechanism of reduction of interstitial levels due toC implant is believed to be as follows: C in substitutional orinterstitial positions reacts with interstitial Si atoms. The C-Si pairsare either complexed with other C atoms or diffuse out from the highconcentration interstitial region. This causes a reduction in theoverall concentration of interstitials thereby reducing the level ofdislocations that may be formed. C implantation into the sub-collectorregion typically occurs prior to C implantation into the collectorregion.

[0048] The next step of the present invention is shown in FIG. 4. Inthis figure, SiGe layer 20 is formed on substrate 10 as well as onisolation regions 12. In accordance with a preferred embodiment of thepresent invention, the SiGe layer includes polycrystalline Si regions 24that are formed predominately over isolation regions 12, andsingle-crystal SiGe layer 22 that is formed predominately over thesub-collector region. The single-crystal SiGe region further includesextrinsic SiGe base regions 29 and intrinsic SiGe base region 26. Theextrinsic base region is an implanted region which can be formed byeither a blanket ion implantation process or a combined patterning/ionimplantation process. The SiGe layer is formed epitaxially utilizing awell-known deposition process including, but not limited to: ultra-highvacuum chemical vapor deposition (UHVCVD) and rapid thermal chemicalvapor deposition (RTCVP).

[0049] It is again emphasized that the present invention is not limitedto the embodiment wherein the SiGe layer is formed by epitaxialdeposition. Note that when epi processes are employed the SiGe layer isformed with extrinsic base regions abutting the intrinsic base region.The present invention also contemplates cases wherein the extrinsic baseregions are formed during the deposition of the SiGe layer utilizing theprocesses mentioned above.

[0050] To reduce dislocations at the base region, a second Cimplantation step, as shown in FIG. 5, is performed. Specifically, ithas been determined that C implantation into both the extrinsic baseregions and the collector-base junction region reduces the level ofdislocations present in the structure. The second C implantation stepwhich implants C into the extrinsic SiGe base regions is carried outusing a C dose of from about 1E13 to about 1E16 cm⁻² and an implantationenergy of from about 5 to about 200 keV. More preferably, the second Cimplantation step is carried out using a C dose of about 1E14 cm⁻² andan implantation energy of about 15 keV. The same or different C sourceas used in the first C implantation step may be used in the secondcarbon implantation step. Note that in some embodiments, the secondimplant step, i.e., C implant into the extrinsic base regions, may beomitted.

[0051] An N-type dopant implant (not shown) may optionally be carriedout in the pedestal, i.e., collector-base junction region 27, and/orcollector region 16 at this point of the inventive method so as to forma device which operates at high-speeds. The optional N-type dopantimplant is carried out using conventional processing techniques that arewell known to those skilled in the art including, for example, ionimplantation and activation annealing. It is noted that during thisimplant step, dislocations may also form in the structure causing shortsdue to implantation damage caused by the implant. The region where thisoccurs in is typically just below the intrinsic SiGe base region.

[0052] Next, and as shown in FIG. 6, an insulator layer 30 is formed onSiGe base layer 20 utilizing a conventional deposition process such asCVD, plasma-assisted CVD, chemical solution deposition and other likedeposition processes. The insulator may be a single layer, as is shownin FIG. 6, or it may contain multi-insulator layers. Insulator layer 30is composed of the same or different insulator material which isselected from the group consisting of SiO₂, Si oxynitride and other likeinsulators.

[0053] Emitter opening 31 is then formed in insulator layer 30 so as toexpose a portion of the intrinsic base region, See FIG. 7. The emitteropening is formed utilizing lithography and etching. The etching stepused is selective in removing the insulator material as compared to theSiGe layer. At this point of the present invention, C may be implantedinto collector-base junction region 27, also referred to in the art as apedestal region of the device, using a third C ion implantation processthat is carried out using a C dose of from about 1E13 to about 1E16 cm⁻²and at an energy of from about 5 to about 200 keV. More preferably, thethird C implant is carried out at a C dose of about 1E14 cm⁻² and anenergy of about 50 keV. Note that the third C implant step includes theuse of the same or different C source as the first C implant step andthat in some embodiments the third implant may be omitted.

[0054] Following formation of the emitter opening, emitter polysiliconlayer 32 is formed on the insulator layer and in the emitter opening byutilizing a conventional deposition process such as CVD. The emitterpolysilicon and the insulator are then selectively removed so as to formemitter region 28 on the SiGe base region, See FIG. 1. Specifically,lithography and etching are employed in forming the structure shown inFIG. 1. It is should be noted that a single etching process may beemployed in removing portions of emitter polysilicon layer 32 andinsulator layer 30, or separate etching steps may be employed inremoving these layers.

[0055] Conventional BiCMOS processing steps may then be performed on thestructure shown in FIG. 1. Note that emitter diffusion region 34 isformed in the intrinsic base region 26 during a subsequent annealingstep.

[0056] While this invention has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present invention. It is therefore intended that the presentinvention not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

Having thus described our invention in detail, what we claim is new anddesire to secure by the Letters Patent is:
 1. A method of improving theSiGe bipolar yield of a semiconductor heterojunction bipolar transistorcomprising the steps of: (a) providing a structure which includes atleast a bipolar device region, said bipolar device region comprising atleast a collector region formed over a sub-collector region, and a SiGelayer formed over said collector and subcollector regions, said SiGelayer comprising at least an intrinsic base region and a collector-basejunction region, wherein said intrinsic base region is abutted byextrinsic base regions; and (b) implanting C into at least one region ofsaid structure selected from said collector, said sub-collector, saidextrinsic base regions and said collector-base junction region.
 2. Themethod of claim 1 wherein all four regions are implanted with C.
 3. Themethod of claim 1 wherein step (b) includes a source of carbon.
 4. Themethod of claim 3 wherein said source of C is CO₂.
 5. The method ofclaim 1 wherein said collector region is implanted with said C using a Cdose of from about 1E13 to about 1E16 cm⁻² and an implantation energy offrom about 5 to about 200 keV.
 6. The method of claim 5 wherein saidcollector region is implanted with said C using a C dose of about 1E14cm⁻² and an implantation energy of about 20 keV.
 7. The method of claim1 wherein said sub-collector region is implanted with said C using a Cdose of from about 1E13 to about 1E16 cm⁻² and an implantation energy offrom about 10 to about 1000 keV.
 8. The method of claim 7 wherein saidsub-collector region is implanted with said C using a C dose of about1E14 cm⁻² and an implantation energy of about 400 keV.
 9. The method ofclaim 1 wherein said extrinsic base regions are implanted with said Cusing a C dose of from about 1E13 to about 1E16 cm⁻² and an implantationenergy of from about 5 to about 200 keV.
 10. The method of claim 9wherein said extrinsic base regions are implanted with said C using a Cdose of about 1E14 cm⁻² and an implantation energy of about 15 keV. 11.The method of claim 1 wherein said collector-base junction region isimplanted with said C using a C dose of from about 1E13 to about 1E16cm⁻² and an implantation energy of from about 5 to about 200 keV. 12.The method of claim 11 wherein said collector-base junction region isimplanted with said C using a C dose of about 1E14 cm⁻² and animplantation energy of about 20 keV.
 13. A method of improving the SiGebipolar yield of a semiconductor heterojunction bipolar transistorcomprising the steps of: (a) providing a structure which includes atleast a bipolar device region, said bipolar device region comprising atleast a collector region formed over a sub-collector region; (b)implanting C into said collector and said sub-collector regions; (c)forming a SiGe layer on said bipolar device region, said SiGe layercomprising at least an intrinsic base region and a collector-basejunction region, wherein said intrinsic base region is abutted byextrinsic base regions; (d) implanting C into said extrinsic baseregions; (e) forming an insulator layer on said SiGe layer; (f)providing an emitter opening in said insulator layer so as to expose aportion of said intrinsic base region and implanting C through saidemitter opening and through the exposed portion of said intrinsic baseregion into the collector-base junction region; and (g) forming anemitter polysilicon region on said insulator layer, including in saidemitter opening.
 14. The method of claim 13 wherein said collectorregion is implanted with said C using a C dose of from about 1E13 toabout 1E16 cm⁻² and an implantation energy of from about 5 to about 200keV.
 15. The method of claim 14 wherein said collector region isimplanted with said C using a C dose of about 1E14 cm⁻² and animplantation energy of about 20 keV.
 16. The method of claim 13 whereinsaid sub-collector region is implanted with said C using a C dose offrom about 1E13 to about 1E16 cm⁻² and an implantation energy of fromabout 10 to about 1000 keV.
 17. The method of claim 16 wherein saidsub-collector region is implanted with said C using a C dose of about1E14 cm⁻² and an implantation energy of about 400 keV.
 18. The method ofclaim 13 wherein step (c) comprises a deposition process.
 19. The methodof claim 18 wherein said deposition process is an ultra-high vacuumchemical vapor deposition (UHVCVD) process.
 20. The method of claim 13wherein said extrinsic base regions are implanted with said C using a Cdose of from about 1E13 to about 1E16 cm⁻² and an implantation energy offrom about 5 to about 200 keV.
 21. The method of claim 20 wherein saidextrinsic base regions are implanted with said C using a C dose of about1E14 cm⁻² and an implantation energy of about 15 keV.
 22. The method ofclaim 13 wherein said collector-base junction region is implanted withsaid C using a C dose of from about 1E13 to about 1E16 cm⁻² and animplantation energy of from about 5 to about 200 keV.
 23. The method ofclaim 22 wherein said collector-base junction region is implanted withsaid C using a C dose of about 1E14 cm⁻² and an implantation energy ofabout 20 keV.
 24. A SiGe heterojunction bipolar transistor which hasimproved SiGe bipolar yield comprising: a semiconductor substrate of afirst conductivity type including at least a sub-collector region and acollector region; a SiGe base layer formed on said substrate, said SiGebase layer comprising at least a collector-base junction region formedover the collector region and an intrinsic base region, wherein saidintrinsic base region is abutted by extrinsic base regions; and anemitter region formed on a portion of said intrinsic base region, saidemitter region comprising at least an emitter polysilicon region,wherein at least one region of said structure selected from saidcollector, said sub-collector, said extrinsic base regions and saidcollector-base junction region includes a C implant.
 25. The SiGeheterojunction bipolar transistor of claim 24 wherein said substrate isa semiconducting material selected from the group consisting of Si, Ge,SiGe, GaAs, InAs, InP and layered semiconductors.
 26. The SiGeheterojunction bipolar transistor of claim 25 wherein saidsemiconducting material is Si.
 27. The SiGe heterojunction bipolartransistor of claim 24 wherein said substrate further includes isolationregions.
 28. The SiGe heterojunction bipolar transistor of claim 27wherein said isolation regions are LOCOS regions or trench isolationregions.
 29. The SiGe heterojunction bipolar transistor of claim 24wherein said SiGe base layer is an epi-SiGe layer.
 30. The SiGeheterojunction bipolar transistor of claim 29 wherein said SiGe baselayer includes polycrystalline SiGe regions abutting a single-crystalSiGe region.
 31. The SiGe heterojunction bipolar transistor of claim 24wherein said emitter region includes a patterned insulator layer. 32.The SiGe heterojunction bipolar transistor of claim 31 wherein saidpatterned insulator layer is composed of an insulator material selectedfrom the group consisting of SiO₂, Si oxynitride and multi-layersthereof.
 33. The SiGe heterojunction bipolar transistor of claim 24further comprising digital logic circuitry formed adjacent thereto. 34.A SiGe heterojunction bipolar transistor comprising: bipolar transistorcomprises: a semiconductor substrate of a first conductivity typeincluding at least a sub-collector region and a collector region whichare both doped with implanted C; a SiGe base layer formed on saidsubstrate, said SiGe base layer comprising at least a collector-basejunction region formed over the collector region, an intrinsic baseregion, and extrinsic base regions abutting said intrinsic base region,wherein said collector-base junction region and said extrinsic baseregions are doped with implanted C; and an emitter region formed on aportion of said intrinsic base region, said emitter region comprising atleast an emitter polysilicon region.